With conventional metal-insulator-metal (MIM) processes, there are poor planarization issues at the copper (Cu) area and low-dielectric constant (low-k) damage issues. A low-k damage and loss issue also occurs during ash for the polymer removal and photoresist strip.
U.S. Pat. No. 6,528,384 B2 to Beckmann et al. describes a method for manufacturing a trench capacitor.
U.S. Pat. No. 6,495,874 B1 to Kawamura et al. describes a semiconductor device and production process thereof.
U.S. Pat. No. 6,384,442 B1 to Chen describes a fabrication process for metal-insulator-metal capacitor with low gate resistance.
U.S. Pat. No. 6,346,454 B1 to Sung et al. describes a method of making dual damascene interconnect structure and metal electrode capacitor.